Freescale Semiconductor /MKE14Z7 /LPSPI1 /TCR

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Interpret as TCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FRAMESZ0 (00)WIDTH 0 (00)TXMSK 0 (0)RXMSK 0 (0)CONTC 0 (0)CONT 0 (0)BYSW 0 (0)LSBF 0 (00)PCS0 (000)PRESCALE 0 (0)CPHA 0 (0)CPOL

LSBF=0, CONTC=0, CONT=0, PCS=00, CPOL=0, CPHA=0, PRESCALE=000, BYSW=0, TXMSK=00, WIDTH=00, RXMSK=0

Description

Transmit Command Register

Fields

FRAMESZ

Frame Size

WIDTH

Transfer Width

0 (00): Single bit transfer.

1 (01): Two bit transfer.

2 (10): Four bit transfer.

TXMSK

Transmit Data Mask

0 (00): Normal transfer.

1 (01): Mask transmit data.

RXMSK

Receive Data Mask

0 (0): Normal transfer.

1 (1): Receive data is masked.

CONTC

Continuing Command

0 (0): Command word for start of new transfer.

1 (1): Command word for continuing transfer.

CONT

Continuous Transfer

0 (0): Continuous transfer disabled.

1 (1): Continuous transfer enabled.

BYSW

Byte Swap

0 (0): Byte swap disabled.

1 (1): Byte swap enabled.

LSBF

LSB First

0 (0): Data is transferred MSB first.

1 (1): Data is transferred LSB first.

PCS

Peripheral Chip Select

0 (00): Transfer using LPSPI_PCS[0]

1 (01): Transfer using LPSPI_PCS[1]

2 (10): Transfer using LPSPI_PCS[2]

3 (11): Transfer using LPSPI_PCS[3]

PRESCALE

Prescaler Value

0 (000): Divide by 1.

1 (001): Divide by 2.

2 (010): Divide by 4.

3 (011): Divide by 8.

4 (100): Divide by 16.

5 (101): Divide by 32.

6 (110): Divide by 64.

7 (111): Divide by 128.

CPHA

Clock Phase

0 (0): Data is captured on the leading edge of SCK and changed on the following edge.

1 (1): Data is changed on the leading edge of SCK and captured on the following edge.

CPOL

Clock Polarity

0 (0): The inactive state value of SCK is low.

1 (1): The inactive state value of SCK is high.

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